module DDS_DIV_ADDR
(
	CLKIN,
	ADDRDIS,
	RSTn,
	DIV_PAR,
	CLKOUT,
	ADDROUT
);

	//parameter DDS_DIS = 8'd100; //address 

	input CLKIN;
	input [7:0]ADDRDIS;
	input RSTn;
	input [15:0]DIV_PAR;
	output CLKOUT;
	output [7:0]ADDROUT;
	
	reg addrclk;
	reg [15:0]clkcnt;
	
	wire CLKOUT;
	
	//clock DIV
	always @ (posedge CLKIN or negedge RSTn)
	begin
		if(!RSTn)
		begin
			addrclk <= 0;
			clkcnt  <= 16'd0;
		end
		else if (clkcnt == DIV_PAR)
		begin
			addrclk <= ~addrclk;
		end
		else
		begin
			clkcnt <= clkcnt + 1'b1;
		end
	end
	
	assign CLKOUT = addrclk;
	
	
	wire [7:0]ADDROUT;
	reg  [7:0]addrcnt;
	
	always @ (posedge CLKOUT or negedge RSTn)
	begin
		if(!RSTn)
		begin
			addrcnt <= 8'd0;
		end
		else if(addrcnt == ADDRDIS)
		begin
			addrcnt <= 8'd0;
		end
		else
		begin
			addrcnt <= addrcnt + 1'b1;
		end
	end
	
	assign ADDROUT = addrcnt;

endmodule

		
	